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//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
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//with Mentor Graphics Corporation.                                         //
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//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
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//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
// Standard Configuration definitions for the M8051EW core Verilog RTL Code
// 
// $Log: m8051ew_cfg.v,v $
// Revision 1.3  2002/01/09
// first clean Verilog for version 2
//
// Revision 1.1  2001/12/24
// V2 tidy ups
//
//
////////////////////////////////////////////////////////////////////////////////
//
// Purpose      : M8051EW core reference configuration parameters
//
////////////////////////////////////////////////////////////////////////////////

//-----------------------------------------------------------------------------
//-- Peripheral Selection
//-----------------------------------------------------------------------------
`define ExcludeUART          
// Omit serial interface logic
//`define ExcludeTimers        
// Omit Counter/Timers 0,1,2 
//`define ExcludeTimer2        
// Omit Counter/Timer 2
//`define ExcludePorts         
// Omit I/O port registers and sampling logic

//------------------------------------------------------------------------------
//-- Data Pointer Extensions
//------------------------------------------------------------------------------
// Mapped_DataPointers : When defined, a second address-mapped data pointer is
//                       included in the design at addresses 84h and 85h.
// Banked_DataPointers : When Mapped_DataPointers is undefined, this integer sets
//                       the number of banked datapointers that are included in
//                       the design.  Banked_DataPointers may be set 
//                       to values 0, 1, 2, or 3 to select 1, 2, 4, or 8 data
//                       pointers respectively.

//`define MappedDataPointers   
// Instantiate two memory mapped data pointers
`define BankedDataPointers 0  
// Instantiate 1 (value 0), 2( value 1), 4(value 2), or 8(value 3) banked data pointers

//------------------------------------------------------------------------------
//-- Interrupt Extensions
//------------------------------------------------------------------------------
`define ExtraInterrupts      
// introduce nine extra interrupt sources
`define ExtraPriorities      
// four levels of interrupt prioritisation

//------------------------------------------------------------------------------
//-- Memory Interface Configuration
//------------------------------------------------------------------------------
//`define MemExtend     
// Enable 20-bit addressing
`ifdef MemExtend         // declare address bus width as a macro.
   `define AddrSize 20
`else
   `define AddrSize 16
`endif
//`define TRACE_DEPTH 0 // select OCI Trace memory depth, if zero undefine it
`define TRIG_NUM 1   // select number of OCI triggers
//`define sync_pmem    
// select synchronous program memory interface
//`define sync_iram    
// select synchronous internal data memory interface
//`define muxed_pxram  
// select multiplexed program and external data memory interface
